1. Field of the Invention
This invention relates in general to a semiconductor memory device and, more particularly, to a semiconductor memory device having a sense amplifier improved for a high speed operation.
2. Description of the Background Art
Although present invention is applicable both to a read only memory (ROM) and to a random access memory (RAM), the description is made by way of applying the invention to a ROM hereinafter.
FIG. 3 is a circuit diagram showing a conventional mask ROM. In this figure, an example of the mask ROM having only 16 memory cells is shown for simplifying the description. Referring to FIG. 3, this mask ROM includes an array of memory cell 11 having 16 memory cells 15, a row decoder 22 connected for receiving row address signals A0 and A1, a column decoder 24 connected for receiving column address signals A2 and A3, and a current type sense amplifier 1 for amplifying signals read out from the memory cell 15.
Word line drivers 20 for driving word lines 13 are connected between the outputs of the row decoder 22 and the array of memory cells 11. A column selector 38 is connected between the array of memory cells 11 and a sense amplifier 1. The column selector 38 includes four NMOS transistors connected between each bit line 14 and the input of the sense amplifier 1. These four transistors are turned on selectively responsive to output signals from the column decoder 24.
In operation, the row decoder 22 is responsive to the address signals A0 and A1 to set one of the word lines 13 to a high level. The column decoder 24 is responsive to the address signals A2 and A3 to turn on one transistor in the Y gate 38. As a result, data signals stored in one of the 16 memory cells are applied via Y gate 38 to the input of the sense amplifier 1. The sense amplifier 1 amplifies this signal to output the amplified signal.
FIG. 4 is a circuit diagram showing an example of the conventional current type sense amplifier. This sense amplifier may be seen for example in pages 70 and 71 of the Digest of Technical Papers of the IEEE International Solid State Circuits Conference held in 1987.
Referring to FIG. 4, the sense amplifier 1 includes an inverter 2 connected to an input node N1, a charge supply circuit 4 responsive to the output voltage of the inverter 2 to charge the node N1 to a predetermined potential, and an output circuit 3 responsive to the output voltage of the inverter 2 to output the amplified signal. The inverter 2 includes a PMOS transistor Q4 and an NMOS transistor Q5 connected in series between a source potential Vcc and a ground potential. Each of the transistors Q4 and Q5 has its gate connected together to the input node N1. The charge supply circuit 4 includes an NMOS transistor Q8 connected between the source potential Vcc and the node N1. The transistor Q8 has its gate connected to an output node of the inverter 2, referred to hereinafter as node N2. The output circuit 3 includes a PMOS transistor Q6 and an NMOS transistor Q7 connected in series between the source potential Vcc and the node N1. The transistor Q6 has its gate connected to the ground potential. The transistor Q7 has its gate connected to the node N2. The output signal of this sense amplifier 1 is outputted via a common connection node of the transistors Q6 and Q7.
In FIG. 4, for illustrating the operation of the sense amplifier 1, four of the memory cells Q1, Q2, Q11 and Q12 of the array of memory cells 11 are shown. The bit line BL1 connected to the transistors Q1 and Q2, is connected to the input node N1 of the sense amplifier 1 via NMOS transistor Q3 constituting the Y gate circuit. Similarly, the bit line BL11, connected to the transistors Q11 and Q12, is connected to the node N1 via the NMOS transistor Q13.
In a mask ROM, data signals to be stored in the ROM are written during in the manufacture process. The writing methods includes for example contact writing method in which data are written depending on whether or not a window for connection to the drain of the field effect transistor constituting the memory cell and an ion implantation writing method in which data are written by selectively forming a depletion type transistor or on enhancement type transistor by ion implantation. No matter which of the methods is applied, the data signals written in the memory cells are read out by sensing whether the transistor constituting the selected memory cell is turned on or not. In the following description, it is assumed that, when a memory cell is selected, the data "0" is stored in the memory cell when the transistor therein is turned on and the data "1" is stored in the memory cell when the transistor is turned off.
The operation of this prior art circuit is hereinafter explained. In the following description, it is assumed that the data "1" is stored in the memory cell including the transistor Q1, and that the data "0" is stored in the memory cell including the transistor Q2.
The operation in the sense amplifier 1 before the start of the readout operation, that, is, before the when the transistor Q3 and Q13 are turned off, is first explained. When the node N1 is at a low level potential, transistor Q4 is turned on, while transistor Q5 is turned off. Thus, the inverter 2 outputs a high level voltage to set the node N2 to a high level. Transistors Q7 and Q8 are turned on responsive to the voltage at the node N2. When the transistor Q8 is turned on, the potential at the node N1 starts to be increased. In the inverter 2, the transistors Q4 and Q5 are turned off and on, respectively, responsive to the increased potential at the node N1. As a result, when the voltage at the node N2 is decreases to a voltage lower than the sum of the voltage at the node N1 and the threshold voltage Vth of the transistor Q8, the transistor Q8 is turned off. Hence, the potential at the node N2 ceases to be increased and, responsive thereto, the potential at the node N2 also ceases to be lowered. The potential at the node N1 at this time is expressed as V01, while that of the node N2 is expressed as V02.
On the other hand, when the node N1 is set to a potential higher than V01, the inverter 2 affords a potential lower than V02 to the node N2. Since the transistors Q7 and Q8 are turned off responsive to the voltage lower than V02, the potential at the node N1 is not changed.
It is seen from the foregoing that, before the read out operation, the node N1 is set to the potential not lower than V01, and the node N2 is brought to the potential not higher than V02.
It is now explained that the bit line in general is previously brought to the low level potential. For example, when the memory cell including the transistor Q12 is accessed, a high level voltage is applied from the row decoder to the word line WL2. The transistor Q12 is turned on or off on the basis of the stored data signal. On the other hand, the transistor Q2 is also turned on, since the signal "0" is stored in the memory cell including the transistor Q2. As a result, the bit line BL1 is connected to the ground potential via transistor Q2. In general, since the array of memory cells 11 includes at least some memory cells in which data signals "0" are stored, the majority of the bit lines are usually brought in advance to the low level potential.
FIG. 5 is a timing chart for illustrating the read out operation by the sense amplifier shown in FIG. 4. Referring to FIGS. 4 and 5, the read out operation may be explained for the case in which the data signals stored in the memory cell including the transistor Q1 and the memory cell including the transistor Q2 are read out sequentially from these memory cells.
When the transistor Q1 is accessed, the word line WL1 is brought to the high level by the row decoder, while the column decoder outputs a high level signal Y1. The transistor Q3 is turned on responsive to the signal Y1. The transistor Q1 is not capable of being turned on since the data "1" is stored therein. Since the bit line BL1 is brought previously to the low level potential, the bit line BL1 is charged rapidly by the sense amplifier 1 after the transistor Q3 is turned on. Thus, the potential at the node N1 is lowered temporarily. Since the potential at the node N2 is responsive to the changes in the potential of the node N1 to be increased temporarily by the inverter 2, transistor Q8 is responsive thereto to be turned on. With the transistor Q8 turned on, the node N1 and the bit line BL1 are charged rapidly. As the potential at the node N1 is increased by this charging, the potential at the node N2, increased temporarily as described above, starts rapidly to be lowered under the operation of the inverter 2. Since the inverter 2 outputs the inverted voltage with a delay, the potential at the node N2 is not lowered to V02 when the potential at the node N1 reaches V01. Hence, the transistor Q8 remains ON, so that the node N1 is charged further and brought to a potential higher than V01. When the potential at the node N2 is lowered by the inverter 2 to V02, transistor Q8 is turned off. At this time, the node N1 is already brought to a potential exceeding V01. Responsive to the voltage at the node N1 at this time, the channel resistance of the transistor Q4 is high and the channel resistance of the transistor Q5 is low, as compared to the case in which the potential at the node N1 is V01. As a result, the charges at the node N2 are discharged via transistor Q5 and the potential at the node N2 is lowered to the vicinity of the ground level.
The output circuit 3 is responsive to the voltage at the node N2 to output a high level output signal So.
This state is not changed even after transistor Q3 is turned off. Although it is assumed in the above example that the node N1 is at the potential of V01 in the initial state, the potential at the node N1 after the charging of the bit line BL1 is approximately equal to that of the present example even when the voltage at the node N1 is at a potential higher than V01. It is because the parasitic capacitance on the bit line BL1 is sufficiently large as compared to the capacitance proper to the node N1.
The case of the transistor Q2 being accessed after this state is explained. For accessing the transistor Q2, the word line WL2 is brought to the high level by the row decoder, while the column decoder outputs a high level signal Y1. The transistor Q3 is turned on responsive to the signal Y1. Since the transistor Q2 is also turned on responsive to the voltage applied to the word line WL2, there is formed a current path connecting the node N1 to the ground potential by way of transistor Q3, bit line BL1 and transistor Q2. Thus the potential at the node N1 and the bit line BL1 is lowered. The inverter 2 is responsive to the potential at the node N1 to raise the potential at the node N2. As a result, transistors Q8 and Q7 are turned on and the output circuit 3 outputs a low level output signals So.
As described above, the node N2 was brought to close to the ground potential by previously accessing the transistor Q1, so that, when transistor Q2 is accessed, it takes some time until the potential at the node N2 is raised by the inverter 2. As a result, the transistor Q7 in the output circuit 3 is turned on with a delay, that is, as shown in FIG. 5, a longer time is elapsed since the rising of the voltage at the word line W2 or the output signal Y1 of the column decoder until the falling of the output signal So. This means that the readout speed is low.
A prior art technology having particular interest to the present invention is seen in the Japanese Patent Laying Open No. 130492/1983. In this prior art, a sense amplifier is disclosed. This sense amplifier includes a circuit for previously maintaining an input node of the sense amplifier connected to the bit line, that is, the node corresponding to the node N1 shown in FIG. 4, at a predetermined potential.